Job Description and Requirements
Candidate should be B.E/ME in Electrical , Electronics or Computer Science Engineering. Should have good understanding in Digital electronics. Candidate would be working as a part of Synopsys Verification Groups Product Engineering Team.
- Content Planning
- Planning and executing both unit level and block level validation, run & debug the test failures, report analysis, regression management
- Improvement of verification test suites to qualify & Sign off our Verification Tool Releases.
- Collateral Improvement
- Good knowledge on programming languages System Verilog/Verilog/VHDL is must
- Knowledge on Perl/Python would be a big plus.
- Hands-on experience in simulation, front end verification is preferred.
- Proficiency in functional verification, testcases creation, simulation using VCS or other simulators, debugging wing with Verdi/DVE, familiarity with scripting languages is plus.
- Good Communication skills are must
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