ASIC Digital Verification Engineer – Mixed Signal IP 154 views

Job Id E1980710
Job Title ASIC Digital Verification Engineer – Mixed Signal IP
Post Date 02/10/2020
Company Qualcomm Technologies, Inc.
Job Area Engineering – Verification
Location India – Bangalore
Job Overview QCT is currently seeking digital verification engineers for the mixed-signal IPs that support QCTs mobile platforms. Successful candidates will be working on the following: Digital Verification Engineer for PLL, DAC, ADC and other mixed-signal designs. Block level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level. The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
Minimum Qualifications Bachelor’s degree in Science, Engineering, or related field.
4+ years ASIC design, verification, or related work experience 
Preferred Qualifications Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation, score-boarding and coverage closure. Mixed-Signals IPs require creation, maintenance and debugging of analog circuits behavioral models. Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target Assertion and formal verification. Test bench bug tracking and regression mechanism. Formal verification with abstraction model for end-to-end checking. Self-motivated, good communicator, quick learner and good team player. Display positive attitude and demonstrate flexibility in day-to-day work.
Education Requirements Required: Bachelor’s, CS or EE
Preferred: Master’s, CS or EE

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