Making Changes to the RTL in Verilog / System Verilog as per the Design Specifications. Compile and Elaborate the RTL in Simulator. Running the Lint / CDC / Low Power Design Checks Releasing the RTL to the SoC as per the Release process Supporting the SoC Integration of the Core.
Bachelor Of Engg in Electronics or equivalent discipline with 3yrs Experience Min.
Experience in designing boolean logic circuits. Experienced in coding with Verilog / System Verilog. Experience in Tool flow for RTL Compilation / Lint Checks / Clock Domain Crossing Checks. Knowledge of STA / LEC is preferred.