- Looking for Design engineers who are conversant with RTL design using System Verilog/SystemC.
- Should be well versed with different areas of digital design, RTL coding, micro-architecture development, Low-power design techniques, simulation, synthesis, scripting.
- Should be a team player who is willing to work with Verif/Back-end/Power/Architecture teams.
- Masters/Bachelors in Electronics Engineering
- Digital design skills (FPGA/ASIC),Low-power aware design , Micro-architecture design skills
- Hardware Description Language: SystemVerilog/Verilog/SystemC
- Scripting Languages – Perl/Python
- Knowledge in Deep Learning would be advantageous, not mandatory
- Team Player