Work to deliver the most competitive design, be it the most complex ASIC design, or a complex graphics or a processor core, to be hardened in the latest process technology.
- Work with chip design team.
- Provide several chip finishing services.
Education & Experience
- BE/B.Tech/M.Tech in Electronics and Communication Engineering/VLSI Design.
- Must have hands-on experience and knowledge of different LPDDR SRAM techniques with respect to attributes like Data Rate (per pin), Density, Interface, Command/Address Bus, Data Bus, Voltage (VDD1/2/CA/Q), I/O Organization, Number of Banks, Pre-fetch, Burst Length, CA ODT, DQ ODT, Package Types etc.
- Must have understanding of memory architectures, critical paths in design, mis-match margin simulations and characterization flows and tools for process nodes 28nm and 45nm.
- Must must have good understanding in generating timing views, validation of data and QA process for release.
- Working experience with characterization tools (e.g. Altos and SiliconSmart) and with Spice simulators (e.g. HSPICE and HSIM and Ultrasim).
- 2+ work experience
- Should have understanding of circuit design concepts for low power CMOS circuits, LPDDR4 and LPDDR3.
- Promising freshers are welcome