Responsible DFT engineer will work with both with IP and integration teams to understand the DFT requirements. Exposure to DFT Concepts (Scan, BIST), JTAG Debuggers. Product characterization and test point optimization.
Be part of a team of designers and verification engineers, working closely with other team members to implement and verify the functionality of a given design element within the context of the block, chip and overall system as well as to design features for the next generation in RTL.
Education & Experience
- B.E. / B. Tech/ M. Tech in Electronics or Electronics & Telecommunication.
- 3 to 5 years work experience.
- Experience of working in complex test-bench/model in Verilog, System Verilog or System C.
- Experience of working on Functional Verification, SoC Verification, Emulation.
- Preferably having experience in architecture such as x86 or ARM domain based SOCs.
- Good in programming: System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language, OVM/UVM Methodology knowledge and experience.
- Must have good knowledge on the verification flows.
- Excellent hands-on debug skills and problem- solving attitude at SoC and system level.
- Must have good communication skills and the ability to work in a team environment.