Job ID: JR0043895
Responsibilities include but not limited to: – Physical design of the cell-based digital layouts of High-speed serial IO or Memory IO designs using RTL2GDSII methods. – Signoff closure of the different blocks of these designs across all flows like Timing/RV/Layout/ESD/HV/Low power verification. – Responsible for signoff quality assurance, release and further optimization of std cell libraries used in designing of these blocks.
Recent graduation or post graduation with B.S./M.S. degree in the fields of computer engineering/science.- Good knowledge of VLSI design concepts especially in the RTL2GDSII domain.- Hands on knowledge in the areas of Floorplanning, Physical design, APR and signoff flows in designing cell based designs.- Team player, with good problem solving and communication skills.- Automation skills in PERL and/or TCL and/or Shell* is an added plus.
Inside this Business Group
Intel’s Information Technology Group (IT) designs, deploys and supports the information technology architecture and hardware/software applications for Intel. This includes the LAN, WAN, telephony, data centers, client PCs, backup and restore, and enterprise applications. IT is also responsible for e-Commerce development, data hosting and delivery of Web content and services.
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