- Job responsibilities include working with the analog IP and chip design team for timing model generation and verification.
- Candidate must be familiar with the analog CMOS development environment and the requirements of various views for integrating analog macros onto the SOC devices.
- Candidate will work on processor based wireless products that are targeting for various applications including IOT.
- Liberty Timing File (LIB) generation for analog/mixed signal blocks
- Interact with analog designer and chip integration team for the Timing model requirements
- Verification of .lib files as per integration requirement and generation of .db files
- Experience with Liberty Timing model generation tools – liberate, liberate-ams or equivalent
- Expertise in automation skills – perl, skill or equivalent
- Understanding of analog macros such as ADC/DAC, PLL, Voltage Regulator, Bandgap, Comparator, others
- Exposure to Cadence ADE and ADE-XL is a plus
- Understanding of custom layout and idea on various physical views will be positive.
- BSEE minimum, MSEE preferred from an accredited engineering school
- 2-5 years of experience working in an IC development environment
- Additional experience in circuit level debug is desirable
- Strong communication skills and the ability to collaborate in a global team is essential