Full Chip Verification Engineer 607 views

Job Description

Xilinx’s SAV Verification group is looking for a Design Verification Engineer to contribute on high speed Memory Controller and PHY/IO IP Verification. The individual will help design, develop and use digital simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, LPDDR, RLDRAM, QDR, HBM Memory Controllers, PHY/IO, and Network On-Chip (NOC) IPs, Subsystem, and SOC designs.

Job Responsibilities

  • Plan verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random and/or directed verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus quality measurements.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Education & Experience

BS/BTech w/ 2 yrs or MS in Electrical Engineering, Computer Engineering or Computer Science.

Required Skills

  • Candidate is expected to be a strong team player with good communication skills and one who is capable to work independently with an eye towards improving overall product quality.
  • Understanding of state of the art digital design and verification techniques, including simulation-based verification flow, assertion and metric-driven verification.
  • Proficiency in System Verilog and UVM, C, Perl, Python and/or other scripting language.
  • Familiarity with verification management tools and understanding of database management particularly as it pertains to regression management.
  • Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, or Cadence IES is a strong plus.
  • Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus.


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