This is an entry-level position in Solution Validation. The primary role is to create tests that exercise the defined SVG Solutions like MDV and Functional Safety.
Additional roles are to validate SVG-wide language interoperability like SV and LP, as well as, validate Design and Verification flows across SVG tools.
A Bachelor’s degree in Electronics Engineering or Computers Science is required. Candidates are expected to have a background in System Verilog RTL design and Verification. Knowledge of UVM driven verification and Low-power verification of designs is a plus. Scripting in PERL or Python, as well as, shell or Tcl Scripting is required.
Good written and verbal skills are required for this role. Candidates will have to work with multiple teams in multiple time zones.