Intern – Software Engineering 1133 views

Job Description

The candidate is expected to have familiarity with C, SV based verification environment and must possess good analytical and communication skills.

Position Requirements

  • BE (Electronics) from a reputed institute
  • Knowledge of Hardware Design, Verification
  • Knowledge in Verilog/System Verilog/UVM/C
  • Knowledge of standard protocols such as USB, Ethernet and DisplayPort” will be helpful
  • Knowledge of development and verification using SV, UVM and C will be a plus.

This position requires leading VIP product development and becoming a technical expert in protocol and standard methodologies such as UVM. The position requires excellent communication skills to interact with multiple product groups within Cadence and the ability to ramp up on new technologies quickly and independently.


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