Job Description and Requirements
- Should be strong in technical concepts, fundamentals, and good team player.
- He/She will be part of SNPS DDR IP implementation team and responsible for the implementation and integration of world class DDR IPs at the cutting edge technology nodes (14nm,10nm and below).
- Timing closure above ~2GHz, mixed signal had macro IP integration,
- Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job.
- This role is for an technical intern so it is preferable to have Awareness / Training with SNPS tools like DC, PT, PT-SI and ICC2.
Educational qualification: Masters/ Bachelors degree in VLSI or Electronics engineering