Designing of integrated circuit layout into Front-end design using HDLs, Verification, and Back-end Design.
- Active role in all different phases of Physical design implementation of SoCs.
- Block level and Full Chip Physical design of complex Chip/IPs.
- STA and Timing Closure activities.
- Complete the Block level/ Chip Level Physical Verification.
- Chip Level Floor Planning and hierarchical design.
Education & Experience
- Bachelors or Masters (Computer/Electronics Engineering)
- 3+ years experience