Sr Verification Engineer 49 views

Job Description

  • Bachelors (Masters) in EE/EC/CS with 5 or Master+4 years digital design verification
  • Extensive experience in ASIC/FPGA design and verification flows.
  • Familiarity with modern verification practices including System Verilog, UVM and assertion based test
  • Experience and knowledge of Processor verification, AXI protocol
  • Expertise in Scripting languages like Perl/Python, etc.
  • Excellent written and verbal communication skills.

Education Requirements

Bachelors or Masters in EE/EC/CS

Years of Experience

Bachelors with 5+ or Masters with 4+years digital design verification

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