Verification Engineer 1142 views

Job description

  • We are hiring for passionate and exceptional engineers who has expertise in Verification.
  • We are looking for experts who are dynamic, self motivated and out-of-the-box thinkers, to join our team.
  • We adopts diversity and great career growth. We are committed in establishing a team that represents a variety of backgrounds, perspectives, and skills.

Position: Verification Engineers (Sr/Lead/Staff/Principal)

Job Location: Bangalore/Hyderabad

Job Description:

As a part of the verification team, ASIC/SoC/IP Verification engineers are responsible for implementing the verification models, integrating the verification environments, develop script based utilities and supportverification activities.

The key functions and responsibilities are the following:

  • Define and Implement the ASIC/SoC/IP verification environment
  • Develop block and system-level test benches and verification environments using Verilog/SystemVerilog, C/C++, SystemC, VMM/OVM/UVM and/or other verification languages as appropriate.
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
  • Work with design and verification teams and provide technical support for verification activities
  • Support the development of verification test plans, test suites and verification activities

Essential Technical Expertise:

  • Experience in ASIC/SoC verification activities and should have participated in successful completion of at least one ASIC/SoC project from Specifications to Silicon.
  • Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC. Good understanding of ARM processor architecture is plus.
  • Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, Low power and processor verification.
  • Must have experience in developing BFM and functional models in Verilog/System Verilog/ OVM/VMM/UVM.
  • Proven experience of the design verification methodologies such as VMM/OVM/UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.
  • Must have experience in Make and proficient in scripting using perl, Tcl, etc.
  • Must have worked on developing verification environment and test cases
  • Must have conducted functional simulations, exposure to functional coverage and bug management schemes.
  • Protocol Knowledge on PCIe, USB2.0/3.0, Ethernet and LPDDR2/DDR3 is added advantage.
  • Self-motivation, flexibility, with strong inter-personal skills.
  • Good communication skills, oral and written.

Please do send us your updated CV along with below details:

Current CTC:

Expected CTC:

Notice period:

Reason for looking change:


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